SRAM (Static Random Access Memory) bit-cell scaling is a challenge in deep sub-nanometer process technology due to, for example, increase in Random Dopant Fluctuation, Gate Work-function Variation, Device Quantization, and Bias Temperature Instability (NBTI) effects. To mitigate the above effects, Assist Circuits are used for SRAM Arrays. Examples of Assist Circuits include Write Assist (WA) and Read Assist (RA) Circuits. Write Assist (WA) Circuit in combination with Read Assist (RA) Circuit may expand the design window. This combination enables an SRAM bit-cell to meet power/performance and process scaling requirements. However, known WA and RA circuits are static in nature and do not take into account changing operating conditions (e.g., voltage, temperature, and frequency). Static WA circuits may result in overall increase in write power consumption, increase in write time, bigger SRAM bit-cell size (i.e., area increase), etc.